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MB9B120J series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf121j data sheet (full production) publication number MB9B120J_ds706 - 00053 revision 2.0 issue date march 3 1 , 201 5 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. d a t a s h e e t MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential notice on data sheet designations spansion inc. issues data sheets with advance information or preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following conditions upon advance information content : this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspe cts of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary doc ument should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document states the current technical specifications regarding the spansion product(s) describe d herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the discla imer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designat ion is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this category: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may be directed to your local sales office. MB9B120J series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf121j data sheet (full production) publication number MB9B120J_ds706 - 00053 revision 2.0 issue date march 3 1 , 201 5 confidential this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. d eems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications t o the valid combinations offered may occur. ? description the mb9b 120 j series are highly integrated 32 - bit microcontrollers dedi cated for embedded controllers with low - power consumption mode and competitive cost . th ese s eries are based on the arm cortex - m3 processor with on - chip flash memory and sram, and have peripheral functions such as various t imers, adcs and communication interfaces (uart, c sio, i 2 c , lin ). the products which are described in this data sheet are placed into type 10 product categories in fm3 family p eripheral m anual . note: arm and cortex are the registered trademar ks of arm limited in the eu and other countries. d a t a s h e e t 2 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? features ? 32 - bit arm cortex - m3 core ? processor version: r2p1 ? up to 72 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management ? on - chip memories [flash memory] ? 64 kbytes ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series on - chip sram is composed of two independent sram (sram0 , sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: 4 kbyte s ? sram1: 4 kbyte s ? multi - function s erial i nterface (max four channels ) ? 2 channels with 16steps9 - bit fifo (ch. 0/ ch. 1 ), 2 channels without fifo (ch. 2/ ch. 5 ) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? various error detection functions available (parity errors, framing errors, and overrun errors) [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [lin] ? lin protocol rev.2.1 supported ? full - duplex double buffer ? master/slave mode supported ? lin break field generate (can be changed 13 - bit to 16 - bit length) ? lin break delimiter generate (can be changed 1 - bit to 4 - bit length) ? va rious error detect functions available (parity errors , framing errors , and overrun errors) [i 2 c] standard - mode (max 100 kbps) / fast - mode (max 400kbps) supported d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 3 confidential ? dma controller ( four channels) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously. ? 4 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbytes) ? transfer mode: block transfer/burst tr ansfer/demand transfer ? transfer data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 ? a/d converter (max 8channels) [ 12 - bit a/d converter ] ? successive approximation type ? conversion time: 1.0 s @ 5 v ? priority conversion available (priority at 2 levels) not included the function to activate a/d by external trigger input ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4steps) ? b ase timer (max eight channels) operation mode is selectable from the followings for each channel . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer ? general - purpose i/o port this series can use its pins as general - purpose i/o ports when they a re not used for peripherals. moreover, the port relocate function is built - in . it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in the po rt relocate function ? up to 23 fast general - purpose i/o ports@32pin package ? some ports are 5v tolerant s ee ? list of pin functions and ? i/o circuit type to confirm the corresponding pins. ? dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel . ? free - running ? periodic (=reload) ? one - shot ? quadrature position/ revolution counter (qprc) ( one channel) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use as the up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 1 6 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers d a t a s h e e t 4 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? multi - function t imer the multi - function timer is composed of the following blocks. ? 16 - bit free - run timer 3 ch . ? input capture 4 ch . ? output compare 6ch . ? a/d activati on compare 1 ch . ? waveform generator 3 ch . ? 16 - bit ppg timer 3ch . the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function ? real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 01 to 99. ? the interrupt function with specifying date and time (year/month/day/hour/minute/second/a day of the week.) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time. ? capable of rewriting the time with continuin g the time count. ? leap year automatic count is available. ? external interrupt controller unit ? up to 7 external interrupt input pin s @ 32 pin package ? include one non - maskable interrupt (nmi) input pin ? watchdog t imer ( two channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a hardware watchdog and a software watchdog. the " hardware " watchdog timer is clocked by the built - in l ow - speed cr oscillator. therefore , the " hardware" watchdog is active in any low - power consumption modes except rtc, s top modes . ? clock and reset [clocks] selectable from five clock sources (2 external oscillator s, 2 built - in cr oscillator , and main pll). ? main clock : 4 mhz to 48 mhz ? sub clock : 32.768 khz ? built - in h igh - speed cr clock : 4 mhz ? built - in l ow - speed cr clock : 100 khz ? main pll clock [resets] ? reset requests from initx pin ? power on reset ? software reset ? watchdog timers reset ? low - v oltage detection reset ? clock super visor reset d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 5 confidential ? clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? if e xternal clock failure (clock stop) is detected, reset is asserted. ? if e xternal frequency anomaly is detected, interrupt or reset is asserted. ? low - voltage consumption detector (lvd) this series include s 2 - stage monitoring of voltage on the vcc pins. when the voltage falls below the voltage that has been set, low - voltage detector generates an i nterrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation ? low - power consumption m ode four low - power consumption modes supported. ? s leep ? t imer ? rtc ? s top ? debug seria l wire debug port (sw - dp) ? unique id unique value of the device ( 41 - bit ) is set. ? power supply wide range voltage: vcc= 2.7 v to 5.5 v d a t a s h e e t 6 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? product lineup ? memory size product name mb9 b f 121j on - chip flash memory 64 kbytes on - chip s ram sram0 4 kbytes sram1 4 kbytes total 8 kbytes ? function product name mb9bf 121j pin count 32 cpu cortex - m3 freq. 72 mhz power supply voltage range 2.7 v to 5.5 v dmac 4 ch . multi - function serial interface (uart/csio/i 2 c) 4 ch. (max) ch.0/ ch. 1 : fifo ch. 2/ ch. 5 : no fifo base timer (pwc/reload timer/pwm/ppg) 8 ch . (max) mf - timer a/d activation compare 1 ch. 1 unit input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 1 ch . dual timer 1 unit real - time clock 1 unit watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 7 pins (max) + nmi 1 i/o ports 23 pins (max) 12 - bit a/d converter 8 ch . ( 1 unit) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function sw - dp unique id yes note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see ? electrical characteristics 4.ac characteristics (3)built - in cr oscillation characteristics for accuracy of built - in cr . d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 7 confidential ? packages product name package mb9bf 121j lqfp: fpt - 32p - m30 (0. 8 mm pitch) ? qfn : lcc - 32p - m 73 (0. 5 mm pitch) ? ? : supported note: see ? package dimensions for detailed information on each package. d a t a s h e e t 8 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? pin assignment ? fpt - 32 p - m3 0 (top view) d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 9 confidential ? lcc - 32 p - m 73 (top view) d a t a s h e e t 10 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? list of pin functions ? list of p in n umbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin n o pin name i/o circuit type pin state type 1 p3a f k rto00_0 (ppg00_0) frck0_0 int07_0 tioa0_1 sck2_0 (scl2_0) subout_2 rtcco_2 2 p3b f j rto01_0 (ppg00_0) ic00_0 tioa1_1 sot2_0 (sda 2 _ 0 ) 3 p3c f k rto02_0 (ppg02_0) ic01_0 int18_2 tioa2_1 sin2_0 4 p3d f j rto03_0 (ppg02_0) ic02_0 tioa3_1 sck5_1 (scl5_1) ain1_0 5 p3e f k rto04_0 (ppg04_0) int19_2 tioa4_1 sot5_1 (sda5_1) bin1_0 d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 11 confidential pin n o pin name i/o circuit type pin state type 6 p3f f j rto05_0 (ppg04_0) tioa5_1 sin5_1 zin1_0 7 vcc - - 8 c - - 9 vss - - 10 pe2 a a x0 11 pe3 a b x1 12 initx b c 13 p46 d f x0a dtti0x_0 int07_1 14 p47 d g x1a int14 _ 2 15 md0 h d 16 pe0 c e md1 17 p11 g * m an01 sin1_1 int02_1 frck0_2 ain1_2 18 p12 g * l an02 sot1_1 (sda1_1) tioa6_2 ic00_2 bin1_2 d a t a s h e e t 12 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential pin n o pin name i/o circuit type pin state type 19 p13 g * l an03 sck1_1 (scl1_1) subout_1 tiob6_2 ic01_2 rtcco_1 zin1_2 20 p14 g * m an04 sin0_1 int03_1 sck0_1 (scl0_1) ic02_2 21 p15 g * m an05 sot0_1 (sda0_1) int14_0 ic03_2 22 p23 g * l an12 sck0_0 (scl0_0) tioa7_1 dtti0x_1 ain1_1 23 p22 g * l an13 sot0_0 (sda0_0) tiob7_1 zin1_1 24 p21 g * m an14 sin0_0 int06_1 bin1_1 25 vcc - - 26 vss - - d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 13 confidential pin n o pin name i/o circuit type pin state type 27 avrl - - 28 avrh - - 29 p01 e i swclk 30 p03 e i swdio 31 p04 e i swo 32 p0f e h nmix subout_0 crout_1 rtcco_0 *: 5 v tolerant i/o d a t a s h e e t 14 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? list of p in f unctions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the p in. pin function pin name function description pin no adc an01 a/d converter analog input pin. anxx describes adc ch.xx. 17 an02 18 an03 19 an04 20 an05 21 an12 22 an13 23 an14 24 base timer 0 tioa0_1 base timer ch.0 tioa pin 1 base timer 1 tioa1_1 base timer ch.1 tioa pin 2 base timer 2 tioa2_1 base timer ch.2 tioa pin 3 base timer 3 tioa3_1 base timer ch.3 tioa pin 4 base timer 4 tioa4_1 base timer ch.4 tioa pin 5 base timer 5 tioa5_1 base timer ch.5 tioa pin 6 base timer 6 tioa6_2 base timer ch.6 tioa pin 18 tiob6_2 base timer ch.6 tiob pin 19 base timer 7 tioa7_1 base timer ch.7 tioa pin 22 tiob7_1 base timer ch.7 tiob pin 23 debugger swclk serial wire debug interface clock input pin 29 swdio serial wire debug interface data input / output pin 30 swo serial wire viewer output pin 31 external interrupt int02_1 external interrupt request 02 input pin 17 int03_1 external interrupt request 03 input pin 20 int06_1 external interrupt request 06 input pin 24 int07_0 external interrupt request 07 input pin 1 int07_1 13 int14_0 external interrupt request 14 input pin 21 int14 - 2 14 int18_2 external interrupt request 18 input pin 3 int19_2 external interrupt request 19 input pin 5 nmix non - maskable interrupt input pin 32 d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 15 confidential pin function pin name function description pin no gpio p01 general - purpose i/o port 0 29 p03 30 p04 31 p0f 32 p11 general - purpose i/o port 1 17 p12 18 p13 19 p14 20 p15 21 p 21 general - purpose i/o port 2 24 p22 23 p23 22 p3a general - purpose i/o port 3 1 p3b 2 p3c 3 p3d 4 p3e 5 p3f 6 p46 general - purpose i/o port 4 13 p47 14 pe0 general - purpose i/o port e 16 pe2 10 pe3 11 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 24 sin0_1 20 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 23 sot0_1 (sda0_1) 21 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a csio (operation mode 2) and as scl0 when it is used in an i 2 c (operation mode 4). 22 sck0_1 (scl0_1) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a csio (operation mode 2) and as scl0 when it is used in an i 2 c (operation mode 4). 20 multi - function serial 1 sin1_1 multi - function serial interface ch.1 input pin 17 sot1_1 (sda1_1) multi - function serial interface ch.1 output pin . this pin operates as sot1 when it is used in a uart/ csio/ lin (operation modes 0 to 3 ) and as sda1 when it is used in an i 2 c (operation mode 4) . 18 sck1_1 (scl1_1) multi - function serial interface ch.1 clock i/o pin . this pin operates as sck1 when it is used in a csio (operation mode 2) and as scl1 when it is used in an i 2 c (operation mode 4). 19 d a t a s h e e t 16 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential pin function pin name function description pin no multi - function serial 2 sin2_0 multi - function serial interface ch.2 input pin 3 sot2_0 (sda2_0) multi - function serial interface ch.2 output pin . this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). 2 sck2_0 (scl2_0) multi - function serial interface ch.2 clock i/o pin . this pin operates as sck2 when it is used in a csio (operation mode 2) and as scl2 when it is used in an i 2 c (operation mode 4). 1 multi - function serial 5 sin5_1 multi - function serial interface ch.5 input pin 6 sot5_1 (sda5_1) multi - function serial interface ch.5 output pin . this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 5 sck5_1 (scl5_1) multi - function serial interface ch.5 clock i/o pin . this pin operates as sck5 when it is used in a csio (operation mode 2) and as scl5 when it is used in an i 2 c (operation mode 4). 4 multi - function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0. 13 dtti0x_1 22 frck0_0 16 - bit free - run timer ch.0 external clock input pin 1 frck0_2 17 ic00_0 16 - bit input capture input pin of multi - function timer 0. icxx describes channel number. 2 ic00_2 18 ic01_0 3 ic01_2 19 ic02_0 4 ic02_2 20 ic03_2 21 rto00_0 (ppg00_0) waveform generator outpu t pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode. 1 rto01_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode. 2 rto02_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode. 3 rto03_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode. 4 rto04_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode. 5 rto05_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode. 6 d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 17 confidential pin function pin name function description pin no quadrature position/ revolution counter ain1_0 qprc ch.1 ain input pin 4 ain1_1 22 ain1_2 17 bin1_0 qprc ch.1 bin input pin 5 bin1_1 24 bin1_2 18 zin1_0 qprc ch.1 zin input pin 6 zin1_1 23 zin1_2 19 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 32 rtcco_1 19 rtcco_2 1 subout_0 sub clock output pin 32 subout_1 19 subout_2 1 reset initx external reset input pin. a reset is valid when initx="l". 12 mode md0 mode 0 pin. during normal operation, md0="l" must be input. during serial programming to flash memory, md0="h" must be input. 15 md1 mode 1 pin. during serial programming to flash memory, md1="l" must be input. 16 power vcc analog/digital power supply pin 7 vcc analog/digital power supply pin 25 gnd vss analog/digital gnd pin 9 vss analog/digital gnd pin 26 clock x0 main clock (oscillation) input pin 10 x0a sub clock (oscillation) input pin 13 x1 main clock (oscillation) i/o pin 11 x1a sub clock (oscillation) i/o pin 14 crout_1 built - in h igh - speed cr - osc clock output port 32 analog power avrh a/d converter analog reference voltage input pin 28 analog gnd avrl a/d converter analog reference voltage input pin 27 c pin c power supply stabilization capacity pin 8 d a t a s h e e t 18 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? i /o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with s tandby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pul l - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control pull - up resistor digital in put d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 19 confidential type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with s tandby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control n-ch d a t a s h e e t 20 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 21 confidential type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? available to control of pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off h cmos level hysteresis input digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control mode input p-ch p-ch n-ch r d a t a s h e e t 22 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product d esign this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristic s are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with re spect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precau tions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at th e design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. the refore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 3 e d a t a s h e e t march 31 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 23 confidential ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electro magnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices spa nsion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic e nergy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prio r approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packa ging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by defor med pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordanc e with spansion ranking of recommended conditions. d a t a s h e e t 24 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of s emiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause su rfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature ch anges are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive g ases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125c/24 h ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2 ) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other highly static - prone material s for storage of completed board assemblies. d a t a s h e e t march 31 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 25 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor d evices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that wil l adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiatio n or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. http://www.spansion.com/fjdo cuments/fj/datasheet/e - ds/ds00 - 00004.pdf d a t a s h e e t 26 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? handling devices ? power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as lat ch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin and gnd pin , between avrh pin and avrl pin near this device. ? stabilizing supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple ( peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. ? crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such tha t the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. ? sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ? surface mount type size : more than 3.2 mm 1.5 mm load capacitance : approximately 6 p f to 7 pf ? lead type load capacitance : approximately 6 pf to 7 pf d a t a s h e e t march 31 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 27 confidential ? using an external clock when using an external cloc k as an input of the main clock , set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using an external cloc k as an input of the sub clock , set x0 a/ x1 a to the external clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. ? handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disable d . however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. ? c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceram ic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristic s). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. ? mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pi ns is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise . c s device c vss gnd ? example of using an external clock device x0 ( x0a ) x1 (pe3), x1a (p47) can be used as general - purpose i/o ports. set as external clock input d a t a s h e e t 28 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? notes on power - on turn power on/off in the following order or at the same time. turning on : v cc ? serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. ? differences in features among the products with different memory sizes and between flash memory products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to eva luate the electric characteristics. ? pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 29 confidential ? block diagram ? memory size see ? memory size in ? product lineup to confirm the memory size. c o r t e x - m 3 c o r e @ 7 2 m h z ( m a x ) f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 4 c h . c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 7 - p i n + n m i p o w e r o n r e s e t s r a m 0 4 k b y t e s r a m 1 4 k b y t e i d s y s c l k m b 9 b f 1 2 1 j n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r s w c l k , s w d i o x 0 a v r h , a v r l a n x x t i o a x t i o b x c s w o x 1 x 0 a x 1 a s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p x x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r o n - c h i p f l a s h 6 4 k b y t e m u l t i - f u n c t i o n s e r i a l i / f 4 c h . ( w i t h f i f o c h . 0 / c h . 1 ) g p i o p i n - f u n c t i o n - c t r l l v d r o m t a b l e s w - d p m a i n o s c p l l s u b o s c c r 4 m h z c r 1 0 0 k h z l v d c t r l b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . r e a l - t i m e c l o c k r t c c o , s u b o u t u n i t 0 q p r c 1 c h . a i n x b i n x z i n x m u l t i - f u n c t i o n t i m e r 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 1 c h . 1 6 - b i t p p g 3 c h . i c 0 x d t t i 0 x r t o 0 x f r c k x c r o u t s o u r c e c l o c k a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) a h b - a h b b r i d g e m u l t i - l a y e r a h b ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) d a t a s h e e t 30 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? memory map ? memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_1000 0xe000_0000 0x4006_0000 dmac 0x4003_c000 0x4003_b000 rtc 0x4003_9000 0x4003_8000 mfs 0x4400_0000 0x4003_6000 0x4200_0000 0x4003_5000 lvd/ds mode 0x4003_4000 reserved 0x4000_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4003_1000 int-req.read 0x2400_0000 0x4003_0000 exti 0x4002_f000 reserved 0x2200_0000 0x4002_e000 cr trim 0x4002_8000 0x2008_0000 0x4002_7000 a/dc 0x2000_0000 sram1 0x4002_6000 qprc 0x1ff8_0000 sram0 0x4002_5000 base timer 0x4002_4000 ppg 0x0010_0008 0x0010_0000 security/cr trim 0x4002_1000 0x4002_0000 mft unit0 0x4001_5000 dual timer 0x0000_0000 0x4001_3000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved reserved reserved reserved reserved reserved reserved see " ? memory map(2)" for the memory size details. reserved reserved cortex-m3 private peripherals 32mbytes bit band alias peripherals reserved 32mbytes bit band alias reserved reserved reserved flash reserved d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 31 confidential ? memory map (2) * : see "mb9a420l/120l/MB9B120J series flash programming manual" to confirm the detail of flash memory. mb9bf121j 0x2008_0000 0x2000_1000 0x2000_0000 0x1fff_f000 0x0010_0008 0x0010_0004 cr trimming 0x0010_0000 security 0x0000_fff8 0x0000_0000 reserved sram1 4kbytes flash 64kbytes * sa0-7 (8kbx8) reserved reserved sram0 4kbytes d a t a s h e e t 32 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit0 0x4002_1000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff b uilt - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_57ff low - voltage detector 0x4003_5800 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_afff reserved 0x4003_b000 0x4003_bfff real - time clock 0x4003_c000 0x4003_f fff reserved 0x4004_0000 0x4005_ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x41ff_ffff reserved d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 33 confidential ? pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the l level. ? initx=1 this is the period when the initx pin is the h level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 0 . ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 1 . ? input enabled indicates that the input function can be used. ? internal input fixed at 0 this is the status that the input function cannot be used. internal input is fixed at l . ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. d a t a s h e e t 34 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? list of pin status pin status type f unction group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" main crystal oscillator input pin / external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 main crystal oscillator output pin hi - z / internal input fixed at 0 or input enable hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state / when oscillation stop s * 1 , hi - z / internal input fixed at 0 maintain previous state / when oscillation stop s * 1 , hi - z / internal input fixed at 0 maintain previous state / when oscillation stop s * 1 , hi - z / internal input fixed at 0 c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 35 confidential pin status type f unction group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 sub crystal oscillator output pin hi - z / internal input fixed at 0 or input enable hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at 0 maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixe d at 0 h nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected d a t a s h e e t 36 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential pin status type f unction group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 i serial wire debug selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / internal input fixed at 0 j resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected k external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected l analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 37 confidential pin status type f unction group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 m analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than above selected hi - z / internal input fixed at 0 gpio selected *1 : oscillation is stopped at s ub t imer mode , low - speed cr t imer mode, rtc mode, s top mode. *2 : oscillation is stopped at s top mode. d a t a s h e e t 38 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1, * 2 v cc v ss - 0.5 v ss + 6.5 v analog reference voltage* 1, * 3 avrh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( 6.5 v) v v ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage* 1 v ia v ss - 0.5 v cc + 0.5 ( 6.5 v) v output voltage* 1 v o v ss - 0.5 v cc + 0.5 ( 6.5 v) v clamp maximum current i clamp - 2 +2 ma *7 clamp total maximum current [i clamp ] +20 ma * 7 l level maximum output current* 4 i ol - 10 ma 4 ma type 20 ma 12 ma type l level average output current* 5 i olav - 4 ma 4 ma type 12 ma 12 ma type l level total maximum output current i ol - 100 ma l level total average output current* 6 i olav - 50 ma h level maximum output current* 4 i oh - - 10 ma 4 ma type - 20 ma 12 ma type h level average output current* 5 i ohav - - 4 ma 4 ma type - 12 ma 12 ma type h level total maximum output current i oh - - 100 ma h level total average output current* 6 i ohav - - 50 ma power consumption p d - 350 mw storage temperature t stg - 55 + 150 c *1 : these parameters are based on the condition that v ss = 0 v. *2 : v cc must not drop below v ss - 0.5 v. * 3 : ensure that the voltage does not to exceed v cc + 0. 5 v, for example, when the power is turned on. * 4 : the maximum output current is the peak value for a single pin. * 5 : the average output is the average current for a single pin over a period of 100 ms. * 6 : the total average output current is the average current for all pins over a period of 100 ms. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 39 confidential *7 : ? see ? list of pin functions and ? i/o circuit type about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resist ance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consump t ion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . < warning > semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. r +b input (0v to 16v) protection diode p - ch v cc v cc limiting resistor n - ch v cc analog input digital input digital output d a t a s h e e t 40 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential 2. recommended operating conditions (v ss = avrl = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc 2.7 * 2 5.5 v analog reference voltage avrh 2.7 v cc v avrl v ss v ss v smoothing capacitor c s 1 10 f for regulator * 1 operating t emperature fpt 32p m3 0 , lcc 32 p m 19 t a 40 + 105 c 40 + 85 c * 1 : see ? c pin in ? handling devices for the connection of the smoothing capacitor. *2: in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr (including main pll is used) or built - in low - speed cr is possible to operate only. < warning > the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconducto r devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 41 confidential 3. dc characteristics (1) current rating (v cc = 2.7v to 5.5v , v ss = avrl = 0v , t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks typ max r un mode current i cc v cc pll run mode cpu : 72 mhz , peripheral : 36 mhz instruction on flash 27 35 ma *1 , *5 cpu:72 mhz, peripheral : the clock stops nop operation instruction on flash 18 22 ma *1 , *5 cpu : 72 mhz , peripheral : 36 mhz instruction on ram 23 29 ma *1 high speed cr r un mode cpu/ peripheral : 4 mhz* 2 instruction on flash 2.2 3.1 ma *1 sub r un mode cpu/ peripheral : 32 khz instruction on flash 73 910 a *1 , * 6 low speed cr r un mode cpu/ peripheral : 100k hz instruction on flash 105 930 a *1 s leep mode current i ccs pll s leep mode peripheral : 36 mhz 17 20 ma *1 , *5 high speed cr s leep mode peripheral : 4 mhz* 2 1.3 2.2 ma *1 sub s leep mode peripheral : 32 khz 64 890 a *1 , * 6 low speed cr s leep mode peripheral : 100 khz 80 910 a *1 *1 : when a l l ports are fixed. *2 : when setting it to 4 mhz by trimming. * 3 : t a =+25c, v cc = 5.5 v * 4 : t a =+ 105 c, v cc =5.5 v *5 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) d a t a s h e e t 42 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential (v cc = 2.7v to 5.5v , v ss = avrl = 0v , t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks typ max t imer mode current i cct vcc main t imer mode t a = + 25 c , when lvd is off 3.5 4.1 m a *1 t a = + 105 c , when lvd is off 4.6 m a *1 i cct sub t imer mode t a = + 25 c , when lvd is off 15 45 a *1 t a = + 105 c , when lvd is off 740 a *1 rtc mode current i cc r rtc mode t a = + 25 c , when lvd is off 1 3 39 a *1 t a = + 105 c , when lvd is off 580 a *1 s top mode current i cch s top mode t a = + 25 c , when lvd is off 1 2 33 a *1 t a = + 105 c , when lvd is off 550 a *1 *1: when a l l ports are fixed. * 2 : v cc =5.5 v * 3 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 4 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) ? lvd current ( v cc = 2.7v to 5.5v, v ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max low v oltage detection circuit (lvd) power supply current i cclvd vcc at operation for reset v cc = 5.5v 0.13 0.3 a at not detect at operation for interrupt v cc = 5.5 v 0.13 0.3 a at not detect ? flash memory current ( v cc = 2.7v to 5.5v, v ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma ? a/d convertor current ( v cc = 2.7v to 5.5v, v ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad vcc at operation 0.7 0.9 ma reference power supply current i ccavrh avrh at operation avrh=5.5 v 1.1 1.97 ma at stop avrh=5.5 v 0.1 1.7 a d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 43 confidential (2) pin characteristics (v cc = 2.7v to 5.5v, v ss = avrl = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 v cc 0.8 v cc + 0.3 v 5 v tolerant input pin v cc 0.8 v ss + 5.5 v l level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 v ss 0.3 v cc 0.2 v 5 v tolerant input pin v ss 0.3 v cc 0.2 v h level output voltage v oh 4 ma type v cc 4.5 v , i oh = 4 ma v cc 0.5 v cc v v cc < 4.5 v , i oh = 2 ma 12 ma type v cc 4.5 v , i oh = 12 ma v cc 0.5 v cc v v cc < 4.5 v , i oh = 8 ma l level output voltage v ol 4 ma type v cc 4.5 v , i ol = 4 ma v ss 0.4 v v cc < 4.5 v , i ol = 2 ma 12 ma type v cc 4.5 v , i ol = 12 ma v ss 0.4 v v cc < 4.5 v , i ol = 8 ma input leak current i il 5 + 5 a pull up resistance value r pu pull up pin v cc 4.5 v 33 50 90 k v cc < 4.5 v 180 input capacitance c in other than vcc, vss, avrh , avrl 5 15 pf d a t a s h e e t 44 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential 4. ac characteristics (1) main clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 , x1 v cc 4.5 v 4 48 mhz when crystal oscillator is connected v cc < 4.5 v 4 20 4 48 mhz when using external clock input clock cycle t cylh 20.83 250 ns when using external clock input clock pulse width p wh /t cylh , p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf , t cr 5 ns when using external clock internal operating c lock * 1 frequency f cm 72 mhz master clock f cc 72 mhz base clock (hclk/fclk) f cp0 40 mhz apb0 bus clock* 2 f cp1 40 mhz apb1 bus clock* 2 f cp 2 40 mhz apb2 bus clock* 2 internal operating clock * 1 cycle time t cycc 13.8 ns base clock (hclk/fclk) t cycp 0 25 ns apb0 bus clock* 2 t cycp 1 - - 25 ns apb1 bus clock* 2 t cycp 2 - - 25 ns apb2 bus clock* 2 *1: for more information about each internal operating clock , see chapter 2 - 1 : clock in fm3 family p eripheral m anual . *2: for about each apb bus which each peripheral is connected to , see ? block diagram in this data sheet. x0 d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 45 confidential (2) sub clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a , x1a 32.768 khz when crystal oscillator is connected * 32 100 khz when using external clock input clock cycle t cyll 10 31.25 s when using external clock input clock pulse width p wh /t cyll , p wl /t cyll 45 55 % when using external clock * : see ? s ub crystal oscillator in ? handling devices for the crystal oscillator used. x0 a d a t a s h e e t 46 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential (3) built - in cr oscillation characteristics ? built - in high - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c , 3.6 v < v cc 5.5 v 3.92 4 4.08 mhz when trimming *1 t a =0 c to + 8 5 c , 3.6 v < v cc 5.5 v 3.9 4 4.1 t a = 4 0 c to + 105 c , 3.6 v < v cc 5.5 v 3.88 4 4.12 t a = + 25 c , 2.7 v v cc 3.6 v 3.94 4 4.06 t a = 2 0 c to + 8 5 c , 2.7 v v cc 3.6 v 3.92 4 4.08 t a = 2 0 c to + 10 5 c , 2.7 v v cc 3.6 v 3.9 4 4.1 t a = 4 0 c to + 10 5 c , 2.7 v v cc 3.6 v 3.88 4 4.12 t a = 40 c to + 10 5 c 2.8 4 5.2 when not trimming frequency stabilization time t crwt 30 s *2 * 1 : in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming /temperature trimming . *2: this is time from the trim value setting to stable of the frequency of the h igh - speed cr clock. after setting the trim value, the period when the frequency stability time passes can use the h igh - speed cr clock as a source clock. ? built - in low - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl 50 100 150 k hz d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 47 confidential (4 - 1 ) operating conditions of main pll (in the case of using main clock for input of main pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time * 1 (lock up time) t lock 100 s pll input clock frequency f plli 4 16 mh z pll multiple rate 5 37 multiple pll macro oscillation clock frequency f pllo 75 150 mh z main pll clock frequency* 2 f clkpll 72 mh z * 1 : time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family p eripheral m anual . (4 - 2) operating conditions of main pll (in the case of using built - in h igh - speed cr for input clock of m ain pll ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time * 1 (lock up time) t lock 100 s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiple rate 19 35 multiple pll macro oscillation clock frequency f pllo 72 150 mh z main pll clock frequency* 2 f clkpll 72 mh z * 1 : time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family p eripheral m anual . note: make sure to input to the m ain pll source clock, the h igh - speed cr clock (clkhc) that the frequency / temperature has been trimmed. when setting pll multiple rate, please take the accuracy of the built - in h igh - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection d a t a s h e e t 48 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential (5) reset input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx 500 ns (6) power - on reset timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name value unit remarks min max power supply rising time t vcc r v cc 0 ms power supply shut down time t off 1 ms time until releasing power on reset t prt 0.34 3.15 ms glossary ? vcc_minimum : minimum v cc of recommended operating conditions . ? vd h _minimum : minimum detection voltage (when svhr=00000) of low - v oltage detection reset . see 6 . low - v oltage detection characteristics . 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r e s e t v c c c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e t v c c r 0 . 2 v 0 . 2 v t o f f d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 49 confidential ( 7 ) base timer input timing ? timer input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck , tin) 2 t cycp ns ? trigger input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) 2 t cycp ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which base timer is connected to, see ? block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l d a t a s h e e t 50 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ( 8 ) csio /uart timing ? csio (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sck x master mode 4t cycp 4t cycp ns sck sot delay time t slovi sckx , sotx 30 + 30 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 30 ns sck sin hold time t shixi sckx , sinx 0 0 ns serial clock l pulse width t slsh sckx slave mode 2t cycp 10 2t cycp 10 ns serial clock h pulse width t shsl sckx t cycp + 10 t cycp + 10 ns sck sot delay time t slove sckx , sotx 50 30 ns sin sck setup time t ivshe sckx , sinx 10 10 ns sck sin hold time t shixe sckx , sinx 20 20 ns sck falling time t f sckx 5 5 ns sck rising time t r sckx 5 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi function serial is connected t o , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 51 confidential master mode slave mode t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin t slsh t shsl v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin d a t a s h e e t 52 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? csio (spi = 0, scinv = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp 4t cycp ns sck sot delay time t shovi sckx , sotx 30 + 30 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 30 ns sck sin hold time t slixi sckx , sinx 0 0 ns serial clock l pulse width t slsh sckx slave mode 2t cycp 10 2t cycp 10 ns serial clock h pulse width t shsl sckx t cycp + 10 t cycp + 10 ns sck sot delay time t shove sckx , sotx 50 30 ns sin sck setup time t ivsle sckx , sinx 10 10 ns sck sin hold time t slixe sckx , sinx 20 20 ns sck falling time t f sckx 5 5 ns sck rising time t r sckx 5 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bu s number which multi function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 53 confidential master mode slave mode t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove d a t a s h e e t 54 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? csio (spi = 1, scinv = 0 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp 4t cycp ns sck sot delay time t shovi sckx , sotx 30 + 30 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 30 ns sck sin hold time t slixi sckx , sinx 0 0 ns sot sck delay time t sovli sckx , sotx 2t cycp 30 2t cycp 30 ns serial clock l pulse width t slsh sckx slave mode 2t cycp 10 2t cycp 10 ns serial clock h pulse width t shsl sckx t cycp + 10 t cycp + 10 ns sck sot delay time t shove sckx , s ot x 50 30 ns sin sck setup time t ivsle sckx , sinx 10 10 ns sck sin hold time t slixe sckx , sinx 20 20 ns sck falling time t f sckx 5 5 ns sck rising time t r sckx 5 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi function serial is connected to, see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 55 confidential master mode slave mode *: changes when writing to tdr register t sovli t scyc t shovi v ol v ol v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivsli t slixi sck sot sin t f t r t slsh t shsl t shove v i l v i l v ih v ih v ih v oh * v o l v oh v o l v ih v i l v ih v i l t ivsle t slixe sck sot sin d a t a s h e e t 56 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? csio (spi = 1, scinv = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp 4t cycp ns sck sot delay time t slovi sckx , sotx 30 + 30 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 30 ns sck sin hold time t shixi sckx , sinx 0 0 ns sot sck delay time t sovhi sckx , sotx 2t cycp 30 2t cycp 30 ns serial clock l pulse width t slsh sckx slave mode 2t cycp 10 2t cycp 10 ns serial clock h pulse width t shsl sckx t cycp + 10 t cycp + 10 ns sck sot delay time t slove sckx , s ot x 50 30 ns sin sck setup time t ivshe sckx , sinx 10 10 ns sck sin hold time t shixe sckx , sinx 20 20 ns sck falling time t f sckx 5 5 ns sck rising time t r sckx 5 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi function serial is connected to, see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 57 confidential master mode slave mode ? uart e xternal clock input (ext = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min max serial clock l pulse width t slsh c l = 30 pf t cycp + 10 ns serial clock h pulse width t shsl t cycp + 10 ns sck falling time t f 5 ns sck rising time t r 5 ns t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t shsl v i l v i l v i l v ih v ih t r t f t slsh s ck d a t a s h e e t 58 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ( 9 ) external i nput t iming (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl frckx 2 t cycp * 1 n s free run timer input clock icxx input capture dttixx 2 t cycp * 1 ns wave form generator int xx , nmix *2 2 t cycp + 100 * 1 ns external interrupt , nmi *3 500 ns *1 : t cycp indicates the apb bus clock cycle time . about the apb bus number which , multi - function timer , external interrupt is connected t o , see ? block diagram in this data sheet. *2 : when in r un mode, in s leep mode. * 3 : when in s top mode, in rtc mode, in t imer mode. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 59 confidential (1 0 ) quadrature position/revolution counter t iming (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit min max ain pin h width t ahl 2 t cycp * ns ain pin l width t all bin pin h width t bhl bin pin l width t bll t ime from ain pin h level to bin rise t aubu pc_mode2 or pc_ m ode3 t ime from bin pin h level to ain fall t buad pc_mode2 or pc_mode3 t ime from ain pin l level to bin fall t adbd pc_mode2 or pc_mode3 t ime from bin pin l level to ain rise t bdau pc_mode2 or pc_mode3 t ime from bin pin h level to ain rise t buau pc_mode2 or pc_mode3 t ime from ain pin h level to bin fall t aubd pc_mode2 or pc_mode3 t ime from bin pin l level to ain fall t bdad pc_mode2 or pc_mode3 t ime from ain pin l level to bin rise t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc= 0 zin pin l width t zll qcr:cgsc= 0 t ime from determined zin level to ain/bin rise and fall t zabe qcr:cgsc= 1 time from ain/bin rise and fall time to determined zin level t abez qcr:cgsc= 1 *: t cycp indicates the apb bus clock cycle time . about the apb bus number which quadrature position/revolution counter is connected t o , see ? block diagram in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll d a t a s h e e t 60 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential zin ain/bin zin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 61 confidential (1 1 ) i 2 c t iming (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 0.6 s scl clock l width t low 4.7 1.3 s scl clock h width t high 4.0 0.6 s (repeated) s tart condition setup time scl sda t susta 4.7 0.6 s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data setup time sda scl t sudat 250 100 ns stop condition setup time scl sda t susto 4.0 0.6 s t buf 4.7 1.3 s noise filter t sp 2 t cycp * 4 - 2 t cycp * 4 - ns *1 : r and c l represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it doesn't extend at least l period (t low ) of device's scl signal. *3 : a fast - mode i 2 c bus device can be used on a s tandard - mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4 : t cycp is the a pb bus clock cycle time. about the apb bus number that i 2 c is connected to, see ? block diagram in this data sheet. to use standard - mode , set the apb bus clock at 2 mhz or more to use fast - mode, set the apb bus clock at 8 mhz or more. s cl sda d a t a s h e e t 62 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential (1 2 ) swd t iming (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max swdio setup time t s ws sw c l k , swdio 15 ns swdio hold time t sw h sw c l k , swdio 15 ns swdio delay time t sw d sw c l k , swdio 45 ns note: when the external load capacitance c l = 30 pf. swdio (when input) swclk swdio (when output) sw d d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 63 confidential 5. 12 - bit a/d converter ? electrical characteristics for the a/d converter (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min typ max resolution 12 bit integral nonl inearity 3.0 4.5 lsb a vrh = 2.7 v to 5.5 v differential non linearity 2 .5 3.5 lsb zero transition voltage v z t an xx 15 20 mv full scale transition voltage v fst an xx avrh 15 avrh 20 mv conversion time 1. 0 * 1 s sampling time * 2 t s 0.3 10 s compare clock cycle* 3 t cck 50 1000 ns state transition time to operation permission t stt 1.0 s a nalog input capacity c ain 9.7 pf analog input resistance r ain 1. 5 k v cc 4.5 v 2. 2 v cc < 4.5 v interchannel disparity 4 lsb analog port input leak current an xx 5 a analog input voltage an xx avrl avrh v reference voltage avrh 2.7 v cc v avrl v ss v ss v *1: conversion time is the value of sampling time ( t s ) + compare time ( t c ). the condition of the minimum conversion time is when the value of sampling time: 300 ns , the value of sampling time: 700 n s . ensure that it satisfies the value of sampling time ( t s ) and compare clock cycle ( t cck ). for setting of sampling time and compare clock cycle, see chapter 1 - 1 : a/d converter in fm3 family p eripheral m anual analog macro part . the register setting s of the a / d c onverter are reflected in the operation according to the apb bus clock timing. for the number of the apb bus to which the a/d converter is connected, see ? block diagram . the base clock (hclk) is used to generate the sampling time and the compare clock cycle. *2: a necessary sampling time changes by external impedance. e nsure that it set the sampling time to satisfy ( equation 1 ). *3: compare time ( t c ) is the value of ( equation 2). d a t a s h e e t 64 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time r ain : i nput resistance of a/d = 1.5 k at 4.5 v < v cc < 5.5 v i nput resistance of a/d = 2. 2 k at 2.7 v < v cc < 4.5 v c ain : i nput capacity of a/d = 9.7 pf at 2.7 v < v cc < 5.5 v r ext : output impedance of external circuit (equation 2) t c = t cck 14 t c : compare time t cck : compare clock cycle r ext rin cin r ain c omparator an xx analog input pin c ain analog signal source d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 65 confidential ? definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonl inearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t v nt 1 [lsb] 1lsb 1lsb = v fst C v z t 4094 n : a/d converter digital output value. v z t : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v fst : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch the digital output ch anges from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff avrl avrh avrl avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t d a t a s h e e t 66 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential 6. low - v oltage d etection ch aracteristics (1) l ow - v oltage d etection r eset ( t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr *1 = 0 0000 2.25 2.45 2.65 v when voltage drops released voltage vdh 2.30 2.50 2.70 v when voltage rises detected voltage vdl svhr *1 = 0 0001 2.39 2.60 2.81 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0010 2.48 2.70 2.92 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0100 2.76 3.00 3.24 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0110 3.31 3.60 3.89 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 0111 3.40 3.70 4.00 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 1000 3.68 4.00 4.32 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 1001 3.77 4.10 4.43 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises detected voltage vdl svhr *1 = 0 1010 3.86 4.20 4.54 v when voltage drops released voltage vdh same as svhr = 0000 value v when voltage rises lvd stabilization wait time t lvdw 8160 t cycp * 2 s lvd detection delay time t lvd dl 200 s *1: svhr bit of low - voltage detection voltage control register (lvd_ctl) is reset to svhr = 0 0000 by low voltage detection reset. * 2 : t cycp indicates the apb2 bus clock cycle time. d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 67 confidential ( 2 ) interrupt of l ow - v oltage d etection ( t a = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 0 0100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhi = 0 0110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhi = 0 0111 3.40 3 . 70 4.00 v when voltage drops released voltage vdh 3.50 3 . 8 0 4.10 v when voltage rises detected voltage vdl svhi = 0 1000 3.68 4 . 00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhi = 0 1001 3.77 4 . 10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhi = 0 1010 3.86 4 . 20 4.54 v when voltage drops released voltage vdh 3.96 4. 3 0 4.64 v when voltage rises lvd stabilization wait time t lvdw 8160 t cycp * s lvd detection delay time t lvd dl 200 s *: t cycp indicates the apb2 bus clock cycle time. d a t a s h e e t 68 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential 7. flash memory write/erase ch aracteristics (1) write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter value unit remarks typ max sector erase time 0.3 0.7 s includ es write time prior to internal erase half word (16 bit) write time 16 282 s not including system level overhead time ch ip erase time 2.4 5.6 s includes write time prior to internal erase * : the typical value is immediately after shipment , the maxim u m value is guarantee value under 10,000 cycle of erase/write . (2) w rite cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* * : at average + 85 ? c d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 69 confidential 8. r eturn t ime from l ow - p ower c onsumption m ode (1 ) re turn f actor: i nterrupt the return time from l ow - p ower consumption mode is indicated as follows. it is from receiving the re turn factor to starting the program operation. ? re turn c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max * s leep mode t icnt t cycc s high speed cr t imer mode, main t imer mode, pll t imer mode 43 83 s low speed cr t imer mode 310 620 s sub t imer mode 534 724 s rtc mode, s top mode 278 479 s * : the maximum value depe nds on the accuracy of built - in cr . ? operation example of re turn from l ow - p ower consumption mode ( by external interrupt * ) *: external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t 70 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? operation example of re turn from l ow - p ower consumption mode ( by internal resource interrupt*) *: internal resource i nterrupt is not included in re turn factor by the kind of l ow - p ower consumption mode . notes: ? the return factor is different in each low power consumption modes. see chapter 6 : low power consumption mode and operations of standby modes in fm3 family p eripheral m anual . ? when interrupt recoveries, the operation mode that cpu recov eries depends on the state before the low power consumption mode transition. see c hapter 6 : low power consumption mode in fm3 family p eripheral m anual . i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 71 confidential (2) re turn f actor: r eset the return time from l ow - p ower consumption mode is indicated as follows. it is from releasing reset to starting the program operation. ? re turn c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max * sleep mode t rcnt 149 264 s high speed cr timer mode, main timer mode, pll timer mode 149 264 s low speed cr timer mode 318 603 s sub timer mode 308 583 s rtc mode, stop mode 248 443 s * : the maximum value depends on the accuracy of built - in cr . ? operation example of re turn from l ow - p ower consumption mode ( by initx ) i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t 72 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? operation example of re turn from low power consumption mode ( by internal resource reset *) *: intern al resource reset is not included in re turn fa ctor by the kind of l ow - p ower consumption mode . notes: ? the return factor is different in each low power consumption modes. see chapter 6 : low power consumption mode and operations of standby modes in fm3 family p eripheral m anual . ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low power consumption mode transition. see c hapter 6 : low power consumption mode in fm3 family p eripheral m anual . ? the time during the power on reset/low voltage detection reset is excluded. see (6) power on reset timing in 4. ac characteristics in ? electrical characteristics for the detail on the time during the power on reset/low voltage detection reset. ? when in recovery from reset, cpu changes to the h igh speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the m ain pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 73 confidential ? ordering information part number package mb9bf121jpmc plastic ? lqfp32 (0.8 mm pitch) , 32 pin ( fpt - 32p - m30 ) mb9bf121jwqn plastic ? qfn32 (0.5 mm pitch) , 32 pin ( lcc - 32p - m 73 ) datasheet 74 MB9B120J_ds706-00053-2v0-e, march 31, 2015 confidential ? package dimensions 32-pin plastic lqfp lead pitch 0.80 mm package width package length 7.00 mm 7.00 mm lead shape gullwing sealing method plastic mold mounting height 1.60 mm max 32-pin plastic lqfp (fpt-32p-m30) (fpt-32p-m30) c 7.000.10(.276.004)sq 0.80(.031) "a" 0.10(.004) 9.000.20(.354.008)sq 18 17 24 9 16 25 32 index 0~7 0.600.15 (.024.006) 0.25(.010) 0.100.05 (.004.002) details of "a" part 0.10(.004) * 2009-2010 fujitsu semiconductor limited f32051s-c-1-2 0.20(.008) m 0.35 +0.08 ?0.03 +.003 ?.001 .014 0.13 +0.05 ?0.00 +.002 ?.000 .005 (.063) max 1.60 max (mounting height) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet march 31, 2015, MB9B120J_ds706-00053-2v0-e 75 confidential 32-pin plastic qfn lead pitch 0.50 mm package width package length 5.00 mm 5.00 mm sealing method plastic mold mounting height 0.80 mm max weight 0.06 g 32-pin plastic qfn (lcc-32p-m73) (lcc-32p-m73) c 2013 fujitsu semiconductor limited hmbc32-73sc-1-1 3.200.10 0.400.05 (.016.002) (typ) 0.50(.020) 1pin corner c0.25(c.010) (.010.002) 0.250.05 (.068.004) 3.200.10 (.197.004) 5.000.10 (.030.002) index area (0.20) 0.02 (.197.004) 5.000.10 +0.03 -0.02 +.0012 -.0008 0.750.05 ((.008)) (.0008 ) (.068.004) dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t 76 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential ? major changes page section change results revision 0.1 - - initial release revision 1 . 0 - - preliminary data sheet - - company name and layout design change 2 ? features revised i 2 c operation mode name 4 ? features ? revised channel number of mft a /d activation compare 6 ? product lineup ? revised c hannel number of mft a/d activation compare ? added notes of built - in high speed cr accuracy 7 ? packages ? corrected package code 9 ? pin assignment ? corrected package code 20 ? i/o circuit type ? corrected the remarks of type e and f 29 ? block diagram ? revised channel number of mft a/d activation compare 40,42 ? electrical characteristics 3.dc characteristics (1) current rating ? revised the values of tbd 48 ? electrical characteristics 3.ac characteristics (6)power - on reset timing ? revised the values of tbd 61 ? electrical characteristics 3.ac characteristics (11 ) i 2 c timing ? ? revised i 2 c operation mode name ? revised the value of noise filter ? revised the notes explanation 62 ? electrical characteristics 3.ac characteristics (12) swd timing ? add ed the value of swdio delay time 63 ? electrical characteristics 5. 12 - bit a/d converter electrical characteristics ? ? add ed the value of sampling time ? revised the notes explanation ? revised the value of differential nonlinearity +/ - 2.5lsb +/ - 3.5lsb ? delete d (preliminary value) description 68 ? electrical characteristics 7. flash memory write/erase characteristics ? revised the values of tbd ? revised the notes of erase/write cycles and data hold time ? delete d (target value) description 69,71 ? electrical characteristics 8. return time from low - power consumption mode revised the values of tbd 75 ? package dimensions corrected package code revision 2.0 20 ? i/o circuit type added about +b input 31 ? memory map memory map(2) added the summary of flash memory sector and the note 38, 39 ? electrical characteristics 1. absolute maximum ratings added the clamp maximum current added about +b input 40 ? electrical characteristics 2. recommended operation conditions added the note about less than the minimum power supply voltage 41, 42 ? electrical characteristics 3. dc characteristics (1) current rating changed the table format added main t imer mode current 47 ? electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main pll (4 - 2) operating conditions of main pll added the figure of main pll connection 48 ? electrical characteristics 4. ac characteristics (6) power - on reset timing changed the figure of timing 50 - 57 ? electrical characteristics 4. ac characteristics (8) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 63 ? electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage 73 ? ordering information change d notation of part number d a t a s h e et march 3 1 , 201 5 , MB9B120J_ds706 - 00053 - 2v0 - e 77 confidential d a t a s h e e t 78 MB9B120J_ds706 - 00053 - 2v0 - e, march 3 1 , 201 5 confidential colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed an d manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injur y, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other ab normal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the app licable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may conta in information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out o f the use of the information in this document. copyright ? 2013 - 201 5 cypress all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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